msm: clk: qcom: upstream clock framework support on 10nm MDSS PLL

Configure MDSS DSI PLL using upstream clock framework APIs on 10 nm
PLL driver

Change-Id: Ic5ce623a6767d4f3a273ebbde8747ec35fe23c03
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>