clk: Account for rate differences due to PLL fractional programming

The fabia PLLs only have 16 bits to program the fractional divider
setting. As a result, the configured frequency might be slightly
off from the requested one. Account for that before making rate
change requests to the clock parents.

Change-Id: Iea307d7e18a67b91373e4c780c30062144176ec4
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>