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Commit 1cabdbec authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: Account for rate differences due to PLL fractional programming 



The fabia PLLs only have 16 bits to program the fractional divider
setting. As a result, the configured frequency might be slightly
off from the requested one. Account for that before making rate
change requests to the clock parents.

Change-Id: Iea307d7e18a67b91373e4c780c30062144176ec4
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 5f78b91f

drivers/clk/clk.c

+7 −1
Original line number Diff line number Diff line
@@ -1709,8 +1709,14 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, 
		}

	}



	/*

	 * The Fabia PLLs only have 16 bits to program the fractional divider.

	 * Hence the programmed rate might be slightly different than the

	 * requested one.

	 */

	if ((core->flags & CLK_SET_RATE_PARENT) && parent &&

	    best_parent_rate != parent->rate)

		(DIV_ROUND_CLOSEST(best_parent_rate, 1000) !=

			DIV_ROUND_CLOSEST(parent->rate, 1000)))

		top = clk_calc_new_rates(parent, best_parent_rate);



out: