drm/msm/sde: correct AD4 bypass register setting

Enable SW reset control capability for Apical Iridix core always.
This ensures that when ares and apical_core_sw_reset are ORed together,
the in/out conversion blocks reset first to block propagation of any
potential hazards out of the apical wrapper; also clocks to the
apical core are stopped preventing internal hazards.

Change-Id: I57af405f34d7daf6675c46422afbda0fb541e9ae
Signed-off-by: Ping Li <pingli@codeaurora.org>