Commit 15d64c46 authored Jun 05, 2017 by Ping Li Committed by Gerrit - the friendly Code Review server Jun 08, 2017

drm/msm/sde: correct AD4 bypass register setting



Enable SW reset control capability for Apical Iridix core always.
This ensures that when ares and apical_core_sw_reset are ORed together,
the in/out conversion blocks reset first to block propagation of any
potential hazards out of the apical wrapper; also clocks to the
apical core are stopped preventing internal hazards.

Change-Id: I57af405f34d7daf6675c46422afbda0fb541e9ae
Signed-off-by: Ping Li <pingli@codeaurora.org>

parent 684a7b03

drivers/gpu/drm/msm/sde/sde_hw_ad4.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -202,7 +202,7 @@ static int ad4_mode_setup(struct sde_hw_dspp *dspp, enum ad4_modes mode)
		} else {
		info[dspp->idx].state = ad4_state_run;
		SDE_REG_WRITE(&dspp->hw, dspp->cap->sblk->ad.base + blk_offset,
		0);
		0x100);
		}

		return 0;