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Commit 752115dd authored by Elliott Hughes's avatar Elliott Hughes Committed by Gerrit Code Review
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Merge "Add Silvermont architecture cache sizes"

parents f2c0f328 c27a444e
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+9 −2
Original line number Diff line number Diff line
@@ -17,8 +17,15 @@
 * Contributed by: Intel Corporation
 */

#if defined(__slm__)
/* Values are optimized for Silvermont */
#define SHARED_CACHE_SIZE   (1024*1024)         /* Silvermont L2 Cache */
#define DATA_CACHE_SIZE     (24*1024)           /* Silvermont L1 Data Cache */
#else
/* Values are optimized for Atom */
#define SHARED_CACHE_SIZE   (512*1024)          /* Atom L2 Cache */
#define DATA_CACHE_SIZE     (24*1024)           /* Atom L1 Data Cache */
#endif

#define SHARED_CACHE_SIZE_HALF  (SHARED_CACHE_SIZE / 2)
#define DATA_CACHE_SIZE_HALF    (DATA_CACHE_SIZE / 2)