VT: Mandatory jitter time enlarged as interarrival jitter time

[Problem] VT VMOS lab test fail
[Cause] Packet NAL type has changed from FU-A(28) to single(1 or 5)
        Logic can wait other colleague packets that compose same frame
        if packet indicates it's FU-A type.
        But because now it is single type,
        logic doesn't wait colleague packets.
        So if a variance of packet arrival order increases,
        decoder would draw slices of multiple frame at a time.
[Solution] Enlarge jitter time to wait & collect more slices
           from one frame.
           And move jitter time collecting logic to make more precise
           that compensates the enlarging.

Bug: 259235315
Test: manually verified pass

Change-Id: I184d57c14a9774b186a6bc135ae6bb14377bc7cc
Signed-off-by: Kim Sungyeon <sy85.kim@samsung.com>