Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ae5c0ab2 authored by Negreanu Marius Adrian's avatar Negreanu Marius Adrian Committed by Andrew Boie
Browse files

Extend x86 to have different arch variants 



Author: Negreanu Marius Adrian <adrian.m.negreanu@intel.com>
Author: Andrew Boie <andrew.p.boie@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>

Currently, x86 target only has generic i686 and x86-atom
as arch variants. This patch adds the ability to have
more than two arch variants. Defining a new arch variant
is similiar to ARM targets, by adding a new file in
core/combo/arch/x86. These files also define what
capabilities the targeting CPU has (e.g. having SSE2,
SSE3, etc.).

We define arch variants for Sandy Bridge, Ivy Bridge,
Haswell; upcoming arches can be easily added to this
set with future patches.

Change-Id: Iafbce10d205e860738db4a216ff603f9a84d7311
Signed-off-by: default avatarDaniel Leung <daniel.leung@intel.com>
Signed-off-by: default avatarAndrew Boie <andrew.p.boie@intel.com>
parent 14d43108

core/combo/TARGET_linux-x86.mk

+29 −14
Original line number Diff line number Diff line
@@ -131,7 +131,8 @@ TARGET_GLOBAL_CFLAGS += \ 
			-fstrict-aliasing \

			-funswitch-loops \

			-funwind-tables \

			-fstack-protector

			-fstack-protector \

			-m32



android_config_h := $(call select-android-config-h,target_linux-x86)

TARGET_ANDROID_CONFIG_CFLAGS := -include $(android_config_h) -I $(dir $(android_config_h))
@@ -141,23 +142,37 @@ TARGET_GLOBAL_CFLAGS += $(TARGET_ANDROID_CONFIG_CFLAGS) 
TARGET_GLOBAL_CPPFLAGS += \

			-fno-use-cxa-atexit



# XXX: Our toolchain is normally configured to always set these flags by default

# however, there have been reports that this is sometimes not the case. So make

# them explicit here unless we have the time to carefully check it

#

TARGET_GLOBAL_CFLAGS += -mstackrealign -msse3 -mfpmath=sse -m32

TARGET_GLOBAL_CFLAGS += $(arch_variant_cflags)



# XXX: These flags should not be defined here anymore. Instead, the Android.mk

# of the modules that depend on these features should instead check the

# corresponding macros (e.g. ARCH_X86_HAVE_SSE2 and ARCH_X86_HAVE_SSSE3)

# Keep them here until this is all cleared up.

#

ifeq ($(ARCH_X86_HAVE_MMX),true)

    TARGET_GLOBAL_CFLAGS += -DUSE_MMX -mmmx

endif

ifeq ($(ARCH_X86_HAVE_SSE),true)

    TARGET_GLOBAL_CFLAGS += -DUSE_SSE -msse

endif

ifeq ($(ARCH_X86_HAVE_SSE2),true)

TARGET_GLOBAL_CFLAGS += -DUSE_SSE2

    TARGET_GLOBAL_CFLAGS += -DUSE_SSE2 -msse2

endif

ifeq ($(ARCH_X86_HAVE_SSE3),true)

    TARGET_GLOBAL_CFLAGS += -DUSE_SSE3 -msse3

endif



ifeq ($(ARCH_X86_HAVE_SSSE3),true)   # yes, really SSSE3, not SSE3!

TARGET_GLOBAL_CFLAGS += -DUSE_SSSE3

    TARGET_GLOBAL_CFLAGS += -DUSE_SSSE3 -mssse3

endif

ifeq ($(ARCH_X86_HAVE_SSE4),true)

    TARGET_GLOBAL_CFLAGS += -msse4

endif

ifeq ($(ARCH_X86_HAVE_SSE4_1),true)

    TARGET_GLOBAL_CFLAGS += -msse4.1

endif

ifeq ($(ARCH_X86_HAVE_SSE4_2),true)

    TARGET_GLOBAL_CFLAGS += -msse4.2

endif

ifeq ($(ARCH_X86_HAVE_AVX),true)

    TARGET_GLOBAL_CFLAGS += -mavx

endif

ifeq ($(ARCH_X86_HAVE_AES_NI),true)

    TARGET_GLOBAL_CFLAGS += -maes

endif



# XXX: This flag is probably redundant. I believe our toolchain always sets

core/combo/arch/x86/haswell.mk

0 → 100644
+20 −0
Original line number Diff line number Diff line 
# Configuration for Linux on x86.

# Generating binaries for Haswell processors.

#

ARCH_X86_HAVE_MMX    := true

ARCH_X86_HAVE_SSE    := true

ARCH_X86_HAVE_SSE2   := true

ARCH_X86_HAVE_SSE3   := true

ARCH_X86_HAVE_SSSE3  := true

ARCH_X86_HAVE_SSE4   := true

ARCH_X86_HAVE_SSE4_1 := true

ARCH_X86_HAVE_SSE4_2 := true

ARCH_X86_HAVE_AES_NI := true

ARCH_X86_HAVE_AVX    := true



# CFLAGS for this arch

arch_variant_cflags := \

	-march=core-avx2 \

	-mstackrealign \

	-mfpmath=sse \

core/combo/arch/x86/ivybridge.mk

0 → 100644
+20 −0
Original line number Diff line number Diff line 
# Configuration for Linux on x86.

# Generating binaries for Ivy Bridge processors.

#

ARCH_X86_HAVE_MMX    := true

ARCH_X86_HAVE_SSE    := true

ARCH_X86_HAVE_SSE2   := true

ARCH_X86_HAVE_SSE3   := true

ARCH_X86_HAVE_SSSE3  := true

ARCH_X86_HAVE_SSE4   := true

ARCH_X86_HAVE_SSE4_1 := true

ARCH_X86_HAVE_SSE4_2 := true

ARCH_X86_HAVE_AES_NI := true

ARCH_X86_HAVE_AVX    := true



# CFLAGS for this arch

arch_variant_cflags := \

	-march=core-avx-i \

	-mstackrealign \

	-mfpmath=sse \

core/combo/arch/x86/sandybridge.mk

0 → 100644
+18 −0
Original line number Diff line number Diff line 
# Configuration for Linux on x86.

# Generating binaries for SandyBridge processors.

#

ARCH_X86_HAVE_MMX    := true

ARCH_X86_HAVE_SSE    := true

ARCH_X86_HAVE_SSE2   := true

ARCH_X86_HAVE_SSE3   := true

ARCH_X86_HAVE_SSSE3  := true

ARCH_X86_HAVE_SSE4_1 := true

ARCH_X86_HAVE_SSE4_2 := true

ARCH_X86_HAVE_AVX    := true



# CFLAGS for this arch

arch_variant_cflags := \

	-march=corei7-avx \

	-mstackrealign \

	-mfpmath=sse \

core/combo/arch/x86/x86-atom.mk

+6 −4
Original line number Diff line number Diff line
@@ -8,11 +8,13 @@ ARCH_X86_HAVE_MMX := true 
ARCH_X86_HAVE_SSE   := true

ARCH_X86_HAVE_SSE2  := true

ARCH_X86_HAVE_SSE3  := true



ARCH_X86_HAVE_SSSE3 := true

ARCH_X86_HAVE_MOVBE := true

ARCH_X86_HAVE_POPCNT := false   # popcnt is not supported by current Atom CPUs



# This flag is used to enabled Atom-specific optimizations with our toolchain

#

TARGET_GLOBAL_CFLAGS += -march=atom
 
# CFLAGS for this arch

arch_variant_cflags := \

	-march=atom \

	-mstackrealign \

	-mfpmath=sse \