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Commit ee9687db authored by Rohit Vaswani's avatar Rohit Vaswani
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msm: clock-fsm9900: Set PLL4 rate



Set PLL4 early at 576 MHz and main at 288 MHz

Change-Id: I7c2858ae3869cea08f84bce50a85a3fb7d23ee3b
Acked-by: default avatarKaushik Sikdar <ksikdar@qti.qualcomm.com>
Signed-off-by: default avatarRohit Vaswani <rvaswani@codeaurora.org>
parent 1ff72517
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