clk: qcom: clock-a7: Fix the speed bin logic for efuses

Some targets may support multiple efuse registers to decide upon the speed
bin for selecting the correct speed bin table. Fix the bin falling in '0'
to take the correct shift and mask.

Change-Id: Ib051c8a7116ead64c69f63d1637d0ff5f153cd6b
Signed-off-by: Taniya Das <tdas@codeaurora.org>