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Commit e7888fb8 authored by Xiaogang Cui's avatar Xiaogang Cui Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add coresight byte counter interrupt for msmferrum 



Add device tree entry to support CoreSight byte counter interrupt
feature which raises an interrupt on transfer of programmed
number of bytes to ETR-memory.

Change-Id: I7ebc90427309ffab00f2dbe1b0f320ed7a40ff24
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 079bdbd1
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