ARM: dts: msm: Make APQ8084 USB controllers independent

Previously the primary and secondary USB3 controllers were
defined as parent and child, in order to enforce a dependency
that restricts when runtime suspend could happen, which was
when both controllers are runtime suspended. This restriction
can now be relaxed as the SS PHY driver is now better able to
handle when to enter low power mode. Thus the primary and
secondary USB controllers can now each be independent devices
under the top-level soc node.

In order to support this both controllers must share a shared
SS PHY instance. This is because the actual PHY is in fact
a single hardware block that incorporates both primary and
secondary PHYs. Thus there should be a single device and driver
which knows about the aggregate states of both portions, and
will allow suspend/resume whenever possible using reference
counting. Further, the QSCRATCH registers relating to the
second SSPHY found at the 0xf94f8800 base were either unused or
have no relevance since they are managed by the primary PHY
anyway.

Finally, add a parent-supply property to the gdsc_usb30_sec
regulator device pointing to gdsc_usb30 to ensure that the
primary can't power collapse until secondary has done so.

Change-Id: I3a1c3345954b648cbcbc2932770df9b131a18156
Signed-off-by: Jack Pham <jackp@codeaurora.org>