msm: kgsl: Disable top level hardware clock gating for a430

Due to a HW timing issue, top level HW clock gating is causing
register read/writes to be dropped in adreno a430.
Disable top level HW clock gating to fix this issue. This is
only partial HW clock gating because GPU L1, L2 blocks are still
clock gated.

CRs-fixed: 726036
Change-Id: I3a1c295659a8e51c79b26e30c399d2fa6c3e0cce
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>