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Commit c1f8614c authored by Bar Weiner's avatar Bar Weiner Committed by Stephen Boyd
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usb: otg: Add delay between ASSERT and DEASSERT in clock reset 



If target dont have phy_reset_clk , there is no waiting between
link_clk_reset assert and deassert, which cause the reset to fail.
10 useconds waiting is added.

Change-Id: I34a94710767a3e7bf6b48d28c917129bc9d9767f
Signed-off-by: default avatarBar Weiner <bweiner@codeaurora.org>
parent 1f4cab11
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