scsi: ufs-qcom: enable host controller hardware clock gating

The UTP controller has a number of internal clock gating cells (CGCs).
Internal hardware sub-modules within the UTP controller control the CGCs.
Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
in a specific operation, UTP controller CGCs are by default disabled and
this change enables them (after every UFS link startup) to save some power
leakage.

Change-Id: I47bba62436c5913eb6755e59c36a11fea2e9468f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>