ARM: dts: msm: reduce SDC1 clock frequencies for apq8084

The eMMC spec defines 200MHz as the absolute max supported frequency for
HS200 and HS400 modes. To provide a jitter free clock that meets the
spec the clock plan has been updated to support max frequencies of
192 MHz and 384MHz, hence update the SDC1 supported clocks table to
reflect that.

Change-Id: I86bf400a546d2b3d602b4a40ed750d1dc9aa4c6a
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>