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Commit b544ed99 authored by Junjie Wu's avatar Junjie Wu
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clock-gcc-8994: Add MSS_GPLL0 gate clock



MSS needs to vote for GPLL0 before its output can reach MSS clock
controller. Model this vote bit as gate clock.

Change-Id: Ia13ed3847597ac757734cad9ff62a982c61ef91f
Signed-off-by: default avatarJunjie Wu <junjiew@codeaurora.org>
parent f351234d
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