mmc: msm_sdcc: use DATA_PEND bit for CMD53 write operation

DATA_PEND bit (in MCI_DATA_CTL register) was designed to be used
with CMD24 (WRITE_SINGLE_BLOCK) and CMD25 (WRITE_MULTIPLE_BLOCK) to
automatically start the DPSM (Data Path State Machine) after a normal
(non-error) response is received for CMD24/CMD25. To use this feature,
MCI_DATA_CTL register should be written with the enable bit and the
pending bit asserted before ENABLE bit is set in MCI_CMD register.

Now, SDCC controller on newer chipsets like 8974/9625, supports the
DATA_PEND bit for CMD53 write operations as well.

As of now SDCC driver is not using the DATA_PEND bit for CMD53 write
which means for write operation, driver first sends the write command
to card and then waits for the CMD_RESPOND_END interrupt
and then configures ADM/BAM and DATA_CTL register (with ENABLE bit set)
in interrupt context.

Instead now driver can configure the DPSM (have to set DATA_PEND bit as
well) before configuring CPSM (Command Path State Machine) to send write
command. So basically this will be the configuration sequence if
we use DATA_PEND bit:
	1. Configure ADM/BAM.
	2. Configure DATA_CTL with both DATA_PEND and ENABLE bits set.
	3. Configure MCI_CMD register for sending the write command.

All of the above configuration will now happen at the same time in
process context.

Change-Id: I57f15ecddf0d150cdab78370eb29a622a690bd69
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>