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Commit aceda18e authored by Adrian Salido-Moreno's avatar Adrian Salido-Moreno Committed by Stephen Boyd
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msm: mdss: improve clock and bus scaling logic



Current clock logic only considers panel pixel clock to calculate mdp
clock speed, MDP clock speed should also consider other factors such
as surface scaling. Bus scaling should also consider surface scaling
factor. Update logic to consider these new factors and perform these
performance updates together.

Change-Id: If274a7f40f496e1a730e1d0e8d7c35fa4384a832
Signed-off-by: default avatarAdrian Salido-Moreno <adrianm@codeaurora.org>
parent d7d3f2b5
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