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Commit ac4aab9e authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Sivalatha Chakrala
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msm: mdss: delay clearing the DSI error interrupt 



At present, the DSI error interrupt is cleared before the
respective errors are handled. This might cause re-generation
of the error interrupt which causes the ISR to be scheduled
again. Hence clear the DSI error interrupt after the errors
are handled.

Change-Id: I42b1d0beee8597e60b4103106ebbeffe6caf065e
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent e7743b9b

drivers/video/msm/mdss/mdss_dsi_host.c

+8 −1
Original line number Diff line number Diff line
@@ -2124,6 +2124,7 @@ void mdss_dsi_clk_status(struct mdss_dsi_ctrl_pdata *ctrl) 


void mdss_dsi_error(struct mdss_dsi_ctrl_pdata *ctrl)

{

	u32 intr;



	/* disable dsi error interrupt */

	mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 0);
@@ -2136,6 +2137,12 @@ void mdss_dsi_error(struct mdss_dsi_ctrl_pdata *ctrl) 
	mdss_dsi_status(ctrl);		/* mask0, 0xc0100 */

	mdss_dsi_dln0_phy_err(ctrl);	/* mask0, 0x3e00000 */



	/* clear dsi error interrupt */

	intr = MIPI_INP(ctrl->ctrl_base + 0x0110);

	intr &= DSI_INTR_TOTAL_MASK;

	intr |= DSI_INTR_ERROR;

	MIPI_OUTP(ctrl->ctrl_base + 0x0110, intr);



	dsi_send_events(ctrl, DSI_EV_MDP_BUSY_RELEASE);

}
@@ -2152,7 +2159,7 @@ irqreturn_t mdss_dsi_isr(int irq, void *ptr) 
	}



	isr = MIPI_INP(ctrl->ctrl_base + 0x0110);/* DSI_INTR_CTRL */

	MIPI_OUTP(ctrl->ctrl_base + 0x0110, isr);

	MIPI_OUTP(ctrl->ctrl_base + 0x0110, (isr & ~DSI_INTR_ERROR));



	pr_debug("%s: ndx=%d isr=%x\n", __func__, ctrl->ndx, isr);