msm: pil-q6v5: Stage L2 memory power-ons to decrease inrush current

Powering on the memories all in one write may potentially cause
voltage droop on the memory power-rail. Power them on in individual
writes to avoid this. Inrush events are short enough that no explicit
delay is needed between the writes.

Change-Id: Ia5123fd98c6919d549e434b1af840b22a0e4c9f2
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>