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Commit a571ee18 authored by Patrick Daly's avatar Patrick Daly Committed by Stephen Boyd
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msm: clock-8226: Fix incorrect voltage limit value 



The hw and sw frequency plan rounded the SVS frequency limit for the
vcodec clk to different values.

Change-Id: I721556cbdce7923f287eb733ccf16701ea7d3347
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent e23041d5
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