msm: display: 8092: Update pipe-flush sel reg for VID pipe

For mpq platform, buffer is not queued through HWC except the
first frame. So, added this change to get the correct pipe flush
setting for VIG pipe. Since, in mpq, the buffer is queued
directly by Maple firmware only on VIG pipe. The flag
MDP_VPU_PIPE determines that the layer will be composed by
VPU(maple) on the given pipe.

Change-Id: I0566913d5d14f6160e5cbc132b76ba8fbec609a7
Signed-off-by: Zohaib Alam <zalam@codeaurora.org>