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Commit 96deec9f authored by Susheel Khiani's avatar Susheel Khiani
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ARM: dts: msm: Add SMR register mask bits for context banks for msmferrum



Mask bits are programmed in SMR register's mask bits
field and are used for masking stream id bits which
are irrelevant for SID2CB matching process in SMR
table.

Change-Id: Ied3ab0450210cd419e23604a958103ddc15e87b7
Signed-off-by: default avatarSusheel Khiani <skhiani@codeaurora.org>
parent 30afa84a
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