Loading arch/arm/boot/dts/apq8084-cdp.dtsi +8 −0 Original line number Original line Diff line number Diff line Loading @@ -269,6 +269,14 @@ }; }; gpio@d300 { /* GPIO 20 */ gpio@d300 { /* GPIO 20 */ /* WLAN_3p3v_vreg regulator enable */ qcom,mode = <1>; /* Digital output */ qcom,output-type = <0>; /* CMOS logic */ qcom,invert = <0>; /* Output low initially */ qcom,vin-sel = <0>; /* VPH_PWR */ qcom,src-sel = <0>; /* Constant */ qcom,out-strength = <1>; /* Low */ qcom,master-en = <1>; /* Enable GPIO */ }; }; gpio@d400 { /* GPIO 21 */ gpio@d400 { /* GPIO 21 */ Loading arch/arm/boot/dts/apq8084-regulator.dtsi +8 −0 Original line number Original line Diff line number Diff line Loading @@ -507,4 +507,12 @@ qcom,ldo-disable; qcom,ldo-disable; }; }; }; }; wlan_vreg: wlan_vreg { compatible = "regulator-fixed"; regulator-name = "wlan_vreg"; startup-delay-us = <4000>; enable-active-high; gpio = <&pma8084_gpios 20 0>; }; }; }; Loading
arch/arm/boot/dts/apq8084-cdp.dtsi +8 −0 Original line number Original line Diff line number Diff line Loading @@ -269,6 +269,14 @@ }; }; gpio@d300 { /* GPIO 20 */ gpio@d300 { /* GPIO 20 */ /* WLAN_3p3v_vreg regulator enable */ qcom,mode = <1>; /* Digital output */ qcom,output-type = <0>; /* CMOS logic */ qcom,invert = <0>; /* Output low initially */ qcom,vin-sel = <0>; /* VPH_PWR */ qcom,src-sel = <0>; /* Constant */ qcom,out-strength = <1>; /* Low */ qcom,master-en = <1>; /* Enable GPIO */ }; }; gpio@d400 { /* GPIO 21 */ gpio@d400 { /* GPIO 21 */ Loading
arch/arm/boot/dts/apq8084-regulator.dtsi +8 −0 Original line number Original line Diff line number Diff line Loading @@ -507,4 +507,12 @@ qcom,ldo-disable; qcom,ldo-disable; }; }; }; }; wlan_vreg: wlan_vreg { compatible = "regulator-fixed"; regulator-name = "wlan_vreg"; startup-delay-us = <4000>; enable-active-high; gpio = <&pma8084_gpios 20 0>; }; }; };