iommu: msm: Fix for cache invalidation variance

In some architectures (at least observed on
Cortex-A53), CPU cache invalidation is not just pure
invalidation but clean + invalidation. If the cache
lines are *dirty*, then first clean will happen and DDR
gets updated with cached content and then invalidation
will be performed.

According to the above specification, we cannot just
handover buffer to non-Linux entity before cleaning its
CPU cache lines. Because, later invalidation will
overwrite the DDR content written by non-Linux.

Fix this by doing clean with proper range.

Change-Id: I8b3c6d13961e9e966a2241d5372584f59bdfbcf0
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>