ARM: perf: Add secondary enable/disable functions

Some multi-core ARM chips designate a unique IRQ number for each core for
private peripheral interrupts (PPIs). Others designate a common IRQ number
for all cores. In the latter case, requesting/freeing private peripheral
interrupts currently enables/disables the interrupt for only the executing
core, respectively.

Secondary enable/disable functions should only be defined for chips that
use a PPI for their PMU IRQ. This will enable/disable the PMU IRQ on all
cores after request_irq/free_irq, respectively.

Change-Id: Ia6b0ff4187ef34c5defa8a5bc27553ff8b3d557a
Signed-off-by: Stephen Caudle <scaudle@codeaurora.org>
(cherry picked from commit 7e0b69375543feebbed6a8421f158d48f4aeabb1)

Conflicts:

	arch/arm/kernel/perf_event.c