qcom: clock-cpu-8994: Add voltage voting for the CCI PLL

Although drivers guarantee that the CCI clock will be 'disabled',
i.e., the GPLL0 source will be selected before entering various
deep sleep modes, to respect hardware constraints and to ensure
undervolting does not occur, vote for the SVS voltage level
on VDD_CX when the CCI pll is enabled.

Change-Id: Ia568298520a29adf7511e7ac7b67fcda5e0738a1
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>