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Commit 813f5679 authored by Matt Wagantall's avatar Matt Wagantall Committed by Stephen Boyd
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msm: pil-q6v5: Update QDSP6SS RESET and PWR_CTL registers 



Hardware documentation has been corrected, changing the bit
positions and reset states for this register. Update software
accordingly.

Change-Id: I35ef0e38e9fb64574c74d1082a11af760340f982
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parent c72b4f17
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