i2c-msm-v2: fix potential spinning forever in ISR

IRQ is disabled before doing reset state in
post transfer on timeout to avoid entering ISR that can cause
this issue. If ISR is entered due to transfer error,
waiting for the qup core to get in a valid state may cause watch
dog bite if HW generates NoC error while reading status.
Avoid that by not polling in ISR.

Change-Id: I2e92e43cb37d501a378a717c996b9e98f6cf9fe8
Signed-off-by: Ankit Gupta <ankgupta@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>