ehci: msm-hsic: Add support to disable transaction error counter

CERR is 2bit down error counter that keeps track of number of consecutive
errors detected on single usb transaction. When set to non zero value, hw
decrements the count and updates qTD when transaction fails. If counter
reaches zero, hw marks the qTD inactive and triggers the interrupt. When
CERR is programmed to zero, hw ignores transaction failures. EHCI stack
programs the CERR  to 3 by default. Some peripherals might not work
correctly when CERR is set to 3. Add support to disable CERR in such
platforms.

Change-Id: I750fbe13d70e5f7359c4e1ee1fb649ebe9ec9946
Signed-off-by: Vamsi Krishna <vskrishn@codeaurora.org>