msm: Fix race condition in clearing WDOG_DEBUG_EN during reset

Currently, we assert the PS_HOLD reset immediately after disabling the
debug watchdog enable bit. Because the register writes are to
different register bases, hardware provides no guarantee about which
will occur first. Since the WDOG_DEBUG_EN must be cleared before
PS_HOLD resets the MSM, enforcing the ordering explicitly.

Change-Id: I9699c01bf07740c9cd3e55cbde6c8bb7b91a877b
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>