mtd: msm_nand: Fix wrong uncorrectable error bit check

For the Nand controller on 7x30 and 7x27a, the
uncorrectable error bit in the NANDC_BUFFER_STATUS
register is changed to BIT(8) from BIT(3) (in legacy
targets) due to change in the ECC requirements. Currently,
this is handled only in dual nandc mode (default for 7x30
and 7x27a). In case, if only single nandc is used, the
uncorrectable bit check is broken and the driver wouldn't
detect any ECC errors.

Add software version info in platform data to differentiate
between the targets that have different register interface.

CRs-Fixed: 365433
Change-Id: I3c33ccb0e936e262116dd20798d56530dbae900f
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
(cherry picked from commit ec9b3250fe233e4ff96b4ad23372df5f8299fc67)

Conflicts:

	arch/arm/mach-msm/devices-9615.c
	arch/arm/mach-msm/devices-msm7x27a.c
	arch/arm/mach-msm/devices-msm7x30.c