mmc: sdhci: Fix issues with power IRQ handling

The SDHC core power control IRQ gets triggered when -
* there is a state change in power control bit (bit 0)
  of SDHCI_POWER_CONTROL register.
* there is a state change in 1.8V enable bit (bit 3) of
  SDHCI_HOST_CONTROL2 register.
* Bit 1 of SDHCI_SOFTWARE_RESET is set.

This patch addresses the following 2 issues -

The reset state of 1.8V enable bit in SDHCI_HOST_CONTROL2 is 0
which indicates 3.3V IO voltage. So, when MMC core layer tries to
set it to 3.3V before card detection, the IRQ doesn't get
triggered as there is no state change in this bit. Hence, with
the current code, the VDD IO voltage is never getting set to
3.3V. This patch fixes this issue by setting the VDD IO voltage
to 3.3V whenever SDHC gets powered up.

We get different IRQ ACK status for each of these requests -
power on, power off, IO high, IO low. As of now, the driver is
not considering the IRQ ACK for IO high and IO low requests and
is returing prematurely from check_power_status() based on the
previous ACK for power on/off requests. This is resulting voltage
switch errors during voltage switch sequence for SD/eMMC cards.
This issue is fixed by passing the request type to
check_power_status host op so that driver can wait for its
corresponding ACK from power IRQ.

Change-Id: I07707ac5df731a0d3e4abead28076f0bbbf75c0a
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>