ARM: msm: dts: Enable GPIO 20 high initially during boot-up

QC6174 WLAN Chipset expects the following sequence for PCIe link
initialization:
3.3V -> rising edge WLAN_EN -> PCIe clock

Since PMIC GPIO 20 is configured to output low during kernel
initialization, 3.3V goes down after the SBL initially turns it ON.
3.3V is available again once the vote(s) from CNSS and PCIe
drivers are effective. WLAN_EN GPIO is kept high during this 3.3V
transition; because of that PCIe link initialization fails, QC6174
doesn't see the WLAN_EN rising edge which is the trigger to enable
WLAN module to allow it to take part in PCIe link negotiation.

To fix this, make GPIO 20 high during kernel initialization by
inverting it. Also ensure continued 3.3V supply till kernel
initialization is complete by adding the regulator-boot-on property
to wlan_vreg. This makes sure that 3.3V is kept high before a client
votes for it before kernel initialization completes. If no client
votes for 3.3V before that, kernel will disable 3.3V.

Change-Id: I0740d3acdbf3cc2b1d2baff153cfadd31c27d7c7
Signed-off-by: Sameer Thalappil <sameert@codeaurora.org>