msm: acpuclock-8974: Restrict L2 cache to two perf levels for 8974v1.x

Frequency and voltage sensitivities in some of these early revision
parts cause L2 parity errors to be observed at different frequency
and voltage combinations. 300MHz and 1.5GHz with vdd_mx at 1.05V,
however, is shown to be reliable across all parts.

Restrict L2 scaling to these two performance points for now. This
restriction will be removed for future silicon revisions.

CRs-Fixed: 407593
Change-Id: Ib3eba2f493975a84e7be2067a076f99f86f1246c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>