iommu: msm: Workaround MMU500 active pre-fetch BUG

MMU500 has a bug in active pre-fetch when page table
format is v7S. Details of the BUG are as follows.

If the 2-level mapping is followed by 1MB section mapping at
odd-MB boundary, then any consecutive access across that odd
boundary can cause TLB corruption if these entries are being
active pre-fetched.

                              .
                              .
Even MB boundary     ----------------------------------
                     | Pointer to 2nd level page table |
Odd MB boundary      ----------------------------------
                     | PTE pointing to 1 MB region     |
Even MB boundary     ----------------------------------
                              .
                              .

To workaround this bug, don't allow virtual address at 1MB
alignment. Instead align the buffer at 2MB boundary which
will not reproduce the BUG condition.

If we disable active pre-fetch, BUG would not appear but
that would be huge performance cost that we don't want to
live with.

Change-Id: Ia29299e3d53790a786deee86ee07862277fc4968
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>