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Commit 49f88e6a authored by Kaushal Kumar's avatar Kaushal Kumar Committed by Michael Bohan
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ARM: mm: Set the SMP enable bit for Cortex-A53 



The SMP bit needs to be set in Extended Control Register
of each of the cores for L2 cache coherency in SMP mode.

Change-Id: I909a6cf134cfc595cd2ed4708a753eb36e524f7e
Signed-off-by: default avatarKaushal Kumar <kaushalk@codeaurora.org>
parent 6b34f014
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