i2c-msm-v2: Avoid writing core registers when HW is not ready

SW reset of the qup core can take a few clock-cycles before
getting into valid state. Another register write during that time may
lead to NoC error due to core-master not being reachable by AHB, or
core may return not-ready status if clocks are gated by HW if HW
gated the clocks before SW read the register.
Once core status is valid, make sure core doesn't keep spinning by
sleeping intermittently until timeout, or valid state is reached.

Change-Id: I6bd002bf91ba2221bf8398b92c0e8206d86fe050
Signed-off-by: Ankit Gupta <ankgupta@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>