Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit 49e51c74 authored by Matt Wagantall's avatar Matt Wagantall Committed by Stephen Boyd
Browse files

msm: clock-8610: Add BCR registers for GDSC-collapsible cores



The GDSC driver allows collapse of cores to be disabled
via device tree. Client drivers may still expect the core
to be reset to a clean state after calls to the GDSC APIs,
however.

Specify .bcr_reg addresses for GDSC-collapsible cores so
that the GDSC driver can assert resets to these cores in
lieu of collapsing them.

Change-Id: I45f0e843b84a456482084f0b54a87fa6987ed471
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parent d5598d2c
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment