Merge "Arm: dts: msm: Add csi1 phy clock source to enable csi1 core"

			<&clock_gcc clk_gcc_camss_csi1_clk>,

			<&clock_gcc clk_gcc_camss_csi1pix_clk>,

			<&clock_gcc clk_gcc_camss_csi1rdi_clk>,

			<&clock_gcc clk_gcc_camss_ahb_clk>;

			<&clock_gcc clk_gcc_camss_ahb_clk>,

			<&clock_gcc clk_gcc_camss_csi1phy_clk>;

		clock-names = "ispif_ahb_clk", "camss_top_ahb_clk",

			"csi_ahb_clk", "csi_src_clk",

			"csi_clk", "csi_pix_clk",

			"csi_rdi_clk", "camss_ahb_clk";

		qcom,clock-rates = <80000000 0 0 200000000 0 0 0 0>;

			"csi_rdi_clk", "camss_ahb_clk", "camss_csi1_phy";

		qcom,clock-rates = <80000000 0 0 200000000 0 0 0 0 0>;

	};

	qcom,ispif@1b0a000 {