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Commit 95e4e5f8 authored by Lokesh Kumar Aakulu's avatar Lokesh Kumar Aakulu Committed by Gerrit - the friendly Code Review server
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Arm: dts: msm: Add csi1 phy clock source to enable csi1 core



Add csi1 phy clock for csi1 core clock list

Change-Id: I679e7ece1d1b302306b4c20714a12d8836e9d387
Signed-off-by: default avatarLokesh Kumar Aakulu <lkumar@codeaurora.org>
parent 114f9a73
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+4 −3
Original line number Diff line number Diff line
@@ -78,12 +78,13 @@
			<&clock_gcc clk_gcc_camss_csi1_clk>,
			<&clock_gcc clk_gcc_camss_csi1pix_clk>,
			<&clock_gcc clk_gcc_camss_csi1rdi_clk>,
			<&clock_gcc clk_gcc_camss_ahb_clk>;
			<&clock_gcc clk_gcc_camss_ahb_clk>,
			<&clock_gcc clk_gcc_camss_csi1phy_clk>;
		clock-names = "ispif_ahb_clk", "camss_top_ahb_clk",
			"csi_ahb_clk", "csi_src_clk",
			"csi_clk", "csi_pix_clk",
			"csi_rdi_clk", "camss_ahb_clk";
		qcom,clock-rates = <80000000 0 0 200000000 0 0 0 0>;
			"csi_rdi_clk", "camss_ahb_clk", "camss_csi1_phy";
		qcom,clock-rates = <80000000 0 0 200000000 0 0 0 0 0>;
	};

	qcom,ispif@1b0a000 {