usb: ci13xxx_udc: Do not clear ENDPTSETUPSTAT during USB BUS RESET

When the host sends a setup packet immediately after the bus RESET,
it is possible that due to interrupt latency the USB software observe
both USB BUS Reset Interrupt and USB interrupt for SETUP packet(UI) bits
getting set at the same time. The USB Interrupt SW routine handles the
reset interrupt as it has more priority than UI interrupt and clear the
ENDPTSETUPSTAT register. If the software clears this register, it will
not know that a SETUP packet arrived.

Fix the issue by not clearing the ENDPTSETUPSTAT during usb bus reset
processing. When USB HOST sends SETUP Packet, device controller sends ACK
and sets ENDPTSETUPSTAT bit and asserts USB Interrupt so that SETUP packet
can be correctly read by the software.

CRs-Fixed: 669902
Change-Id: I86656cfcd70d7bc8e1e84604fdbdccc6437c85b6
Signed-off-by: Saket Saurabh <ssaurabh@codeaurora.org>