arm64: Add support for Cortex-A57 Erratum 832075

This Erratum explains the problem that a Cortex-A57 might deadlock
when WB exclusive load/store instructions are mixed with device loads.
An interrupt will break the deadlock.
This erratum requires a particular sequence of the code:
a) A pair of exclusive load and exclusive store instructions.
The exclusive store is to write-back memory location.
b) A branch instruction has a source register which is the same as
the destination register of the older exclusive store.
c) Following the branch instruction, there are six or more loads
to device memory locations

The workaround is to substitute the ldr instruction for load from
device memory to be ldar

Change-Id: I52bdc942aaa93c4b21caf3f9c9b8fe605ec50689
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>