msm: pm: Correct the bit checking for cache type

For ARM v7 the cache size ID register bit 30 indicates
if write back is supported. Currently bit 31 is checked which
is incorrect.

Change-Id: Ic52bbd4f8d9d58468972b9db8539b241ed982712
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>