qseecom: Add clk management

The CE clock was initialized to run at max of 100 MHz.  This
was done during the probe call. Running the CE clk at 100 MHz
always, is causing a power regression.

Fix is to enable the clk and set it to run at the nominal level
of 50 MHz.  Further more, add clk gating to ensure CE clks are only
bumped up to the max of 100 MHz when client request for high bandwidth.

CRs-Fixed: 416759
Change-Id: I311f6b29e9129a04c3ec7e2a8f893fa08a518bbd
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>