clk: qcom: mdss: add mdss 20nm pll clock driver support

Add support for new 20nm PLL clock driver to handle
different DSI panel resolutions. Add seperate files
to support this new 20nm PHY PLL block.

Change-Id: I4ee5309449f317daddba7106cb8e1829fd6e76cf
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>