iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1

Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it
is only applicable to stage-2 context banks.

This patch ensures that we don't set the reserved TCR bits for stage-1
translations.

Change-Id: I7a11a77213ac2a60d6d56bebe7f4a63a83b264c3
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: 1fc870c7efa364862c3bc792cfbdb38afea26742
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>