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Commit 32f2056d authored by Carl Vanderlip's avatar Carl Vanderlip Committed by Stephen Boyd
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arm/dt: msm8974: Increase MDSS clock hysteresis cycles 



Increase the number of cycles the various MDSS clocks (VIG, RGB, DMA, ROT,
DSPP, et al.) stay active for from 4 to 32 cycles.

Change-Id: I291d2c60a01a2e0a5b8e5a5fb640fddc1ab141de
Signed-off-by: default avatarCarl Vanderlip <carlv@codeaurora.org>
parent 994a7873
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