msm: mdss: correct danger safe register programing sequence

Under runs were observed because fill level logic was entering in
dead lock due to faulty register programing sequence. DMA HW clock
gating need to be disabled for fill level logic to work properly.
Fix the panic lut programing and hardware clock gating register
programing sequence.

Change-Id: I8809fdfe7ed936cb2d44b7397448c2c83d856563
Signed-off-by: Ramakant Singh <ramaka@codeaurora.org>